This application relies for priority upon Korean Patent Application No. 2002-12953, filed on Mar. 11, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device for minimizing damage caused by electrostatic discharge and a method of fabricating the same.
Contemporary semiconductor devices constructed of metal-oxide-semiconductor (MOS) transistors are commonly designed to operate at an internal voltage of about 5 volts. When a semiconductor device including such MOS transistors is manually handled or is mounted to an apparatus, static electricity charge existing in the human body or apparatus may inadvertently be applied to the semiconductor device. The human body may discharge an electrostatic voltage at approximately 2000 volts, or, under certain circumstances, more than several tens of thousands of volts. When the ground state of a semiconductor manufacturing apparatus is unstable, the static electricity discharged from the apparatus may be applied to a semiconductor device mounted thereto, causing a large amount of current to flow through the semiconductor device.
If a high-voltage static electricity is applied to a semiconductor device, the MOS transistors may suffer from gate oxide breakdown or junction spiking. These phenomena may cause complete destruction or minute damage to the device, thus diminishing the reliability of the semiconductor device.
To prevent such an electrostatic damage, a circuit for protecting static electricity should be provided along with the functioning circuit. FIG. 1 is a circuit configuration diagram illustrating a typical circuit for protecting a semiconductor chip from an electrostatic discharge pulse at an input pin.
Referring to FIG. 1, a resistor 16 is disposed between an input pin 12 and a functioning circuit 20. A protection device 18 is disposed between the resistor 16 and the input pin 12. Another terminal of the protection device 18 is coupled to a voltage reference pin 14.
Generally, the protection device 18 comprises a transistor having a threshold voltage that is higher than the operation voltage of the functioning circuit 20. For this, the protection device 18 is preferably a field transistor that is connected to the input pin 12 and has a gate and source, and may further comprise a thyrister.
In the event that a high voltage is applied to the input pin 12, the protection device 18 is turned on and a voltage drop occurs at the resistor 16. Thus, the high voltage applied to the input pin 12 may be dissipated through a current path connecting the protection device 18 and the voltage reference pin 14. However, when the voltage applied to the input pin 12 is higher than the voltage level that the protection device 18 is capable of dissipating, the voltage of the input pin 12 may be additionally applied to the functioning circuit 20, which could be catastrophic to the circuit 20. As described above, under these circumstances, although a voltage drop occurs at the resistor 16, the functioning circuit 20 may be attacked.
FIG. 2 is a cross-sectional view illustrating a configuration of a conventional high-voltage transistor formed in the functioning circuit 20 of FIG. 1.
Referring to FIG. 2, a device isolation layer 32 is disposed at a semiconductor substrate 30 of first conductivity type to define an active region. A gate electrode 34 is disposed on the active region and a gate spacer 36 is disposed on sidewalls of the gate electrode 34.
A lightly doped region 38 of a second conductivity type is disposed in the semiconductor substrate 30 beside the gate electrode 34. The lightly doped region 38 may be extended to a lower portion of an edge of the gate electrode 34. A heavily doped region 40 of second conductivity type is disposed in the semiconductor substrate 30 beside the gate spacer 36. At this time, the heavily doped region 40 has a higher concentration and a shallower diffusion depth than the lightly doped region 38. Thus, the heavily and lightly doped regions 40 and 38 constitute a PN junction together with the semiconductor substrate 30. Also, substrate pick-up regions 42 and 44 of first conductivity type are disposed outside the lightly doped region 38 in the semiconductor substrate 30.
An interlayer dielectric (ILD) 46 is disposed on the semiconductor substrate 30 to cover the gate electrode 34 and the gate spacer 36. A contact plug 48, which penetrates the ILD 46 to connect with the heavily doped region 40 and the substrate pick-up regions 42 and 44, is disposed in the ILD 46. An interconnection 50 is disposed on the ILD 46 to connect with the contact plug 48. At this time, the contact plug 48 and the interconnection 50 are normally composed of aluminum.
As explained above with reference to FIG. 1, high voltage due to the static electricity diffused by the protection device 18 may, under certain circumstances, be additionally applied to the functioning circuit 20. Such a high voltage is transferred to the heavily and lightly doped regions 40 and 38 through the interconnection 50 and the contact plug 48. The high voltage may cause a breakdown in the PN junction formed of the lightly and heavily doped regions 38 and 40. Meanwhile, if there is such a breakdown, high-temperature heat is generated at the interface of the PN junction. However, the conventional lightly doped region 38 is too shallow to delay conduction of the high-temperature heat generated at the interface of the contact plug 48. Thus, in the case where the contact plug 48 is composed of aluminum, a material that has a relatively low melting point, the contact plug 48 can melt, which can have catastrophic effect on the product.
It is therefore a feature of the present invention to provide a semiconductor device having a junction region that is structured to mitigate melting of a contact plug due to heat caused by electrostatic discharge.
It is another feature of the present invention to provide a method of fabricating a semiconductor device capable of minimizing degradation of product caused by an electrostatic discharge.
The feature of the present invention can be achieved by a semiconductor device comprising a vertical lightly doped region that increases the effective depth of a junction region connected to an input pin. The device comprises a gate electrode disposed on a semiconductor substrate of a first conductivity type, and a heavily doped region and a vertical lightly doped region, which are formed in the semiconductor substrate on both sides of the gate electrode and are of a second conductivity type. At this time, the vertical lightly doped region has a lower impurity concentration and a greater depth than the heavily doped region.
The vertical lightly doped region surrounds at least one heavily doped region. That is, a junction region where the vertical lightly doped region is formed is connected to an input pin where a high voltage caused by an electrostatic discharge is applied.
Preferably, a horizontal lightly doped region is further disposed at an upper side of the vertical lightly doped region. Here, the horizontal lightly doped region has a lower impurity concentration than the vertical lightly doped region. Also, a gate insulation pattern is further disposed between the gate electrode and the semiconductor substrate, and an insulation pattern may be further disposed between the heavily doped region and an edge of the gate electrode.
Another feature of the present invention can be achieved by a method of fabricating a semiconductor device comprising forming a vertical lightly doped region that increases a depth of a junction region. The method comprises forming a gate electrode on a semiconductor substrate of a first conductivity type. A heavily doped region of second conductivity type is then formed in the semiconductor substrate on sides of the gate electrode. A vertical lightly doped region of a second conductivity type is formed in the semiconductor substrate to surround the heavily doped region. At this time, the vertical lightly doped region is formed to a lower impurity concentration and to a greater depth as compared to the heavily doped region.
It is preferable that forming the vertical lightly doped region is followed by forming the gate electrode. However, the vertical lightly doped region may be formed after forming the heavily doped region.
Forming the heavily doped region preferably uses a spacer as an ion implantation mask.
Preferably, before forming the gate electrode, a horizontal lightly doped region is additionally formed. The horizontal lightly doped region is disposed on upper sidewalls of the vertical lightly doped region and contains impurity ions of the second conductivity type. At this time, it is preferable that the horizontal lightly doped region has a lower impurity concentration than the vertical lightly doped region.
In addition, before forming the gate electrode, a device isolation layer is further formed at a predetermined region of the semiconductor substrate to define an active region. While the device isolation layer is formed, an insulation pattern may be formed between an edge of the gate electrode and the heavily doped region.
Meanwhile, before forming the device isolation layer, a horizontal lightly doped region, which is disposed on upper sidewalls of the vertical lightly doped region and comprises impurity ions of the second conductivity type, may be formed. At this time, the horizontal lightly doped region is formed to have a lower impurity concentration than the vertical lightly doped region.